Architecture of BIST for Memory Testing

A Hybrid BIST Architecture and Its Optimization for SoC Testing

This paper presents a hybrid BIST architecture and methods for optimizing it to test systems-on-chip in a cost effective way. The proposed self-test architecture can be implemented either only in software or by using some test related hardware. In our approach we combine pseudorandom test patterns with stored deterministic test patterns to perform core test with minimum time and memory, without...

A New BIST Architecture for Word Oriented Memory

Systems-on-Chip(SoC)s are now moving from logic dominant to memory dominant chips in order to satisfy high functionality and short development cycle. This means that the yield of memory part is the most important factor for the entire chip yield. In this paper, two word-oriented memory test algorithms are proposed newly. The one is an efficient writing NPSF test algorithm and the other is an ef...

Memory BIST

On-chip Self Testing using BIST-oriented Random Access Memory

The increased circuit density in today’s integrated circuits demands for efficient and low cost testing as compared to the testing of logic with external test equipment. The Built-In Self Test (BIST) architecture provides the self-testing of logic circuit but is not at the positive extreme in delivering deterministic and limited test vectors and storage and compression of output test responses....

Embedded Memory Bist for Systems-on-a-chip Embedded Memory Bist for Systems-on-a-chip

Embedded memories consume an increasing portion of the die area in deep submicron systems-on-a-chip (SOCs). Manufacturing test of embedded memories is an essential step in the SOC production that screens out the defective chips and accelerates the transition from the yield learning phase to the volume production phase of a new manufacturing technology. Built-in self-test (BIST) is establishing ...